I always wanted to get more familiar with Raspberry Pi and Kubernetes. In December during my time off, I finally bought a Pi and experimented few things. One such experiment was to run ASP.NET core web application on Raspberry Pi. This was a fun experiment and I definitely learned more about Raspberry Pi, Kubernetes, ASP.NET core, Traefik, Docker and associated technologies. In this post, I would describe the steps that are required to run ASP.NET web app on Pi.(more…)
I am going to talk about something different from the regular topics in this post. I recently moved one of my old websites to a different hosting provider. As part of that, I worked to make the website responsive. The whole process turned out to be much easier than I thought, and required just few changes. I thought to put them in a post, so it can help anyone else needing the same. Note: I have only tested this in Chrome and Edge on Windows and Android.(more…)
Interrupt handling is one of the critical subsystem in the hypervisor (HV). It is critical both from correctness and performance perspective. Hyper-V supports multi-processor systems and uses many optimizations to improve performance for interrupt virtualization.
Interrupt handling is done via APIC emulation. For each vCPU, a vAPIC is created in the hypervisor. These vAPIC behaves similar to APIC in a physical system and provide interrupt support to virtual machines. To support operating systems that are not APIC aware, PIC emulation is provided using virtual wire mode as specified in Intel multiprocessor specifications.
In this post, I would talk about how interrupts are virtualized in Hyper-V environment and discuss some of the performance optimizations. (more…)
In this series of posts, I am going to talk about interrupt handling in a virtualized environment (specifically Hyper-V). This discussion would also include interrupt handling on systems that have IOMMU based interrupt remapping support. Interrupt remapping is required in Hyper-V for supporting SR-IOV enabled devices and device assignment to virtual machines.
The series is mostly written from software perspective and hardware details are only provided where necessary for understanding of the concepts. The series is focused on x86/x64 based architectures though the concepts described here can be applied to other architectures. (more…)
[Moved an old article that I wrote in 2004 to my new blog]
Windows on 32 bit x86 systems can access up to 4GB of physical memory. This is due to the fact that the processor’s address bus which is 32 lines or 32 bits can only access address range from 0x00000000 to 0xFFFFFFFF which is 4GB. Windows also allows each process to have its own 4GB logical address space. The lower 2GB of this address space is available for the user mode process and upper 2GB is reserved for Windows Kernel mode code. How does Windows give 4GB address space each to multiple processes when the total memory it can access is also limited to 4GB. To achieve this Windows uses a feature of x86 processor (386 and above) known as paging. Paging allows the software to use a different memory address (known as logical address) than the physical memory address. The Processor’s paging unit translates this logical address to the physical address transparently. This allows every process in the system to have its own 4GB logical address space. To understand this in more details, let us first take a look at how the paging in x86 works. (more…)